Siamak Arya

According to our database1, Siamak Arya authored at least 5 papers between 1983 and 1995.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

1995
Evaluation of a branch target address cache.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

An architecture for high instruction level parallelism.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1988
Parallel algorithm development workbench.
Proceedings of the Proceedings Supercomputing '88, Orlando, FL, USA, November 12-17, 1988, 1988

1985
An Optimal Instruction-Scheduling Model for a Class of Vector Processors.
IEEE Trans. Computers, 1985

1983
Optimal Instruction Scheduling for a Class of Vector Processors: an Integer Programming Approach.
PhD thesis, 1983


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