Shyue-Kung Lu

Shih-Chang Huang

IEEE Trans. Very Large Scale Integr. Syst., 2005

A Multi-Faceted Approach towards Spam-Resistible Mail.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

A BIRA algorithm for embedded memories with 2D redundancy.

[BibT_eX]

[DOI]

Yu-Cheng Tsai

Shih-Chang Huang

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

2004

Defect Level Prediction Using Multi-Model Fault Coverage.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors.

[BibT_eX]

[DOI]

Chien-Hung Yeh

Han-Wen Lin

Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs.

[BibT_eX]

[DOI]

Shih-Chang Huang

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model.

[BibT_eX]

[DOI]

Mau-Jung Lu

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Testing and Diagnosis Techniques for LUT-Based FPGA's.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2003

A Novel Built-In Self-Repair Approach for Embedded RAMs.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Combinational circuit fault diagnosis using logic emulation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs.

[BibT_eX]

[DOI]

Fu-Min Yeh

VLSI Design, 2002

OBDD-based evaluation of k-terminal network reliability.

[BibT_eX]

[DOI]

Fu-Min Yeh

Sy-Yen Kuo

IEEE Trans. Reliab., 2002

Enhancing Delay Fault Testability for Iterative Logic Array.

[BibT_eX]

[DOI]

Chien-Hung Yeh

Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks.

[BibT_eX]

[DOI]

Chien-Hung Yeh

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's.

[BibT_eX]

[DOI]

Chung-Yang Chen

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Fault-tolerance design of memory systems based on DBL structures.

[BibT_eX]

[DOI]

Chih-Hsien Hsu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Novel Fault-Tolerant Techniques for High Capacity RAMs.

[BibT_eX]

[DOI]

Chih-Hsien Hsu

Sy-Yen Kuo

Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Built-In self-repair for divided word line memory.

[BibT_eX]

[DOI]

Chih-Hsien Hsu

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A Profit Evaluation System (PES) for logic cores at early design stage.

[BibT_eX]

[DOI]

Tsung-Ying Lee

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Testing Configurable LUT-Based FPGAs.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2000

Built-in self-test and fault diagnosis for lookup table FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Testable/Fault Tolerant FFT Processor Design.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A novel approach to testing LUT-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Defect Level Prediction Using Multi-Model Fault Coverage.

[BibT_eX]

[DOI]

Tsung-Ying Lee

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1997

Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy.

[BibT_eX]

[DOI]

Sy-Yen Kuo

IEEE Trans. Computers, 1997

1996

Cell delay fault testing for iterative logic arrays.

[BibT_eX]

[DOI]

Ruei-Zong Hwang

J. Electron. Test., 1996

1995

C-testable design techniques for iterative logic arrays.

[BibT_eX]

[DOI]

Jen-Chuan Wang

IEEE Trans. Very Large Scale Integr. Syst., 1995

1991

Designing Self-Testable Cellular Arrays.

[BibT_eX]

[DOI]