Shyam Akashe

According to our database, Shyam Akashe authored at least 28 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design.

Vishal Gupta, Sribhuvaneshwari H, Tanmaya Kumar Das, Saurabh Khandelwal, Shyam Akashe

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2018

Design and Enactment of Diverse Low Power Techniques Based Schmitt Trigger.

Mukesh Kumar Singh, Shyam Akashe

Wirel. Pers. Commun., 2018

Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells.

Peter Bukelani Musiiwa, Shyam Akashe

Wirel. Pers. Commun., 2018

2017

Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell.

Shalini Singh, Shyam Akashe

Wirel. Pers. Commun., 2017

2016

FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain-Bandwidth Product Analysis.

Pawan Sharma, Saurabh Khandelwal, Shyam Akashe

Wirel. Pers. Commun., 2016

An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier.

Prateek Jain, Shyam Akashe

Wirel. Pers. Commun., 2016

Design of 8T Volatile and Non-Volatile RAM Cells with Improved Holding Phase Performance.

Peter Bukelani Musiiwa, Shyam Akashe

J. Low Power Electron., 2016

Performance Augmentation of 2: 1 Mux Using Transmission Gate.

Mohit Vyas, Shyam Akashe

ICTCS, 2016

A SDDG FinFET Based Op Amp with DSB Circuit.

Jainendra Tripathi, Ranjeet Singh Tomar, Shyam Akashe

ICTCS, 2016

Power efficient optimal Operational Transconductance Amplifier Using Source Degeneration Technique.

Prateek Tiwari, Ranjeet Singh Tomar, Shyam Akashe

ICTCS, 2016

Design of low power 3-bit TIQ based ADC by using FinFET Technology.

Devansh Sinha, Shyam Akashe

ICTCS, 2016

Novel Gating Technique in D-Latch for Low Power Application.

Akanksha Singh, Ayushi Marwah, Shyam Akashe

ICTCS, 2016

Power and Area Efficient Capacitor Multiplier Technique for Multi-Fin Two Stage Opamp.

Aditya Raj, Shyam Akashe

ICTCS, 2016

Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch.

Peter Bukelani Musiiwa, Shyam Akashe

ICTCS, 2016

Design and Analysis of New Efficient Multifin Low Leakage Switch Mode Power Supply.

Shubham Kumar, Prateek Jain, Shyam Akashe

ICTCS, 2016

Realization of Schmitt Trigger in Low Power SRAM Cell.

Nilotpal Arjun, Ayushi Marwah, Shyam Akashe

ICTCS, 2016

2015

Enhanced Power Gating Schemes for Low Leakage Power and Low Ground Bounce Noise in Design of Ring Oscillator.

Sheetal Soni, Shyam Akashe

Wirel. Pers. Commun., 2015

Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL.

Pooja Joshi, Saurabh Khandelwal, Shyam Akashe

J. Low Power Electron., 2015

High performance 8 bit cascaded carry look ahead adder with precise power consumption.

Raj Johri, Shyam Akashe, Sanjay Sharma

Int. J. Commun. Syst., 2015

2014

Modeling and Analysis of Low Power 10 T Full Adder with Reduced Ground Bounce noise.

Raghvendra Singh, Shyam Akashe

J. Circuits Syst. Comput., 2014

Estimation of high performance in Schmitt triggers with stacking power-gating techniques in 45 nm CMOS technology.

Anshul Saxena, Akansha Shrivastava, Shyam Akashe

Int. J. Commun. Syst., 2014

Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters.

Prateek Jain, Shyam Akashe

Circuits Syst. Signal Process., 2014

2013

Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology.

Shyam Akashe, Sanjay Sharma

Wirel. Pers. Commun., 2013

2012

Analysis and Simulation of Full Adder Design Using MTCMOS Technique.

Richa Saraswat, Shyam Akashe, Shyam Babu

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012

Analyzing and Minimization Effect of Temperature Variation of 2: 1 MUX Using FINFET.

Khushboo Mishra, Shyam Akashe, Satish Kumar

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012

Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 MUX in 45 nm Technology.

Meenakshi Mishra, Shyam Akashe, Shyam Babu

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012

Modeling and Simulation of High Speed 8T SRAM Cell.

Raj Johri, Ravindra Singh Kushwah, Raghvendra Singh, Shyam Akashe

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012

Implementation of 2: 4 DECODER for low leakage Using MTCMOS Technique in 45 Nanometre Regime.

Shyam Akashe, Rajeev Sharma, Nitesh Tiwari, Jayram Shrivas

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012