Shwetha Vijayakumar

According to our database, Shwetha Vijayakumar authored at least 2 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation.

Zihan Yin, Annewsha Datta, Shwetha Vijayakumar, Ajey P. Jacob, Akhilesh Jaiswal

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2021

Augmented Memory Computing: Dynamically Augmented SRAM Storage for Data Intensive Applications.

Haripriya Sheshadri, Shwetha Vijayakumar, Ajey P. Jacob, Akhilesh R. Jaiswal

CoRR, 2021