Shuo Li

Affiliations:
  • Royal Institute of Technology, Stockholm, Sweden (PhD 2015)


According to our database1, Shuo Li authored at least 12 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
System-Level Architectural Hardware Synthesis for Digital Signal Processing Sub-Systems.
PhD thesis, 2015

Physical design aware system level synthesis of hardware.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

2014
Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Three-Dimensional Design Space Exploration for System Level Synthesis.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Case Study: Constraint Programming in a System Level Synthesis Framework.
Proceedings of the Principles and Practice of Constraint Programming, 2014

2013
Memory allocation and optimization in system-level architectural synthesis.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Global Control and Storage Synthesis for a System Level Synthesis Approach.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

System level synthesis of hardware for DSP applications using pre-characterized function implementations.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2011
Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011


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