Shuo Huai

Orcid: 0000-0002-4744-304X

According to our database1, Shuo Huai authored at least 27 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
EvoLP: Self-Evolving Latency Predictor for Model Compression in Real-Time Edge Systems.
IEEE Embed. Syst. Lett., June, 2024

A Fruit-Tree Mapping System for Semi-Structured Orchards Based on Multi-Sensor-Fusion SLAM.
IEEE Access, 2024

FedTR: Federated Learning Framework with Transfer Learning for Industrial Visual Inspection.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Double-Win NAS: Towards Deep-to-Shallow Transformable Neural Architecture Search for Intelligent Embedded Systems.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
An Efficient Gustavson-Based Sparse Matrix-Matrix Multiplication Accelerator on Embedded FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

EdgeCompress: Coupling Multidimensional Model Compression and Dynamic Inference for EdgeAI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

On Hardware-Aware Design and Optimization of Edge Intelligence.
IEEE Des. Test, December, 2023

CRIMP: Compact & Reliable DNN Inference on In-Memory Processing via Crossbar-Aligned Compression and Non-ideality Adaptation.
ACM Trans. Embed. Comput. Syst., October, 2023

LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Latency-constrained DNN architecture learning for edge systems using zerorized batch normalization.
Future Gener. Comput. Syst., May, 2023

SurgeNAS: A Comprehensive Surgery on Hardware-Aware Differentiable Neural Architecture Search.
IEEE Trans. Computers, April, 2023

iMAT: Energy-Efficient In-Memory Acceleration for Ternary Neural Networks With Sparse Dot Product.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Towards Efficient Convolutional Neural Network for Embedded Hardware via Multi-Dimensional Pruning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient in-Memory Acceleration.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

LAMP: Load-Balanced Multipath Parallel Transmission in Point-to-Point NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

EDLAB: A Benchmark for Edge Deep Learning Accelerators.
IEEE Des. Test, 2022

Collate: Collaborative Neural Network Learning for Latency-Critical Edge Systems.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Smart Scissor: Coupling Spatial Redundancy Reduction and CNN Compression for Embedded Hardware.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

You only search once: on lightweight differentiable architecture search for resource-constrained embedded platforms.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Work-in-Progress: What to Expect of Early Training Statistics? An Investigation on Hardware-Aware Neural Architecture Search.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

2021
HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture Search.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2019
Performance-aware Wear Leveling for Block RAM in Nonvolatile FPGAs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019


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