Shunya Nagata

According to our database, Shunya Nagata authored at least 2 papers between 2018 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.

Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications.

Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018