Shunichi Kaeriyama

According to our database, Shunichi Kaeriyama authored at least 11 papers between 2000 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee.

Ken Chang, Shunichi Kaeriyama

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique.

Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno

IEEE J. Solid State Circuits, 2012

High-speed wireline transceivers and clocking.

Gerrit den Besten, Shunichi Kaeriyama

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests.

Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno

IEICE Trans. Electron., 2011

2009

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems.

Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara

IEEE J. Solid State Circuits, 2009

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems.

Yasushi Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007

A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability.

Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Solid-Electrolyte Nanometer Switch.

Naoki Banno, Toshitsugu Sakamoto, Noriyuki Iguchi, Hisao Kawaura, Shunichi Kaeriyama, Masayuki Mizuno, Kazuya Terabe, Tsuyoshi Hasegawa, Masakazu Aono

IEICE Trans. Electron., 2006

2005

Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic.

Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2005

A nonvolatile programmable solid-electrolyte nanometer switch.

Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono

IEEE J. Solid State Circuits, 2005

2000

Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.

Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000