Shunichi Ishiwata

According to our database1, Shunichi Ishiwata authored at least 7 papers between 2002 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis.
IEEE J. Solid State Circuits, 2009

Side Match Distortion based Adaptive Error Concealment order for 1Seg Video Broadcasting Application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007
Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding.
IEICE Trans. Inf. Syst., 2007

2006
Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2003
A single-chip MPEG-2 codec based on customizable media embedded processor.
IEEE J. Solid State Circuits, 2003

2002
A single-chip MPEG-2 codec based on customizable media microprocessor.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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