Shungo Kumazawa
Orcid: 0009-0006-5608-5666
According to our database1,
Shungo Kumazawa
authored at least 7 papers
between 2020 and 2024.
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Bibliography
2024
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access, 2024
IEEE Access, 2024
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024
2023
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023
2021
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training.
Int. J. Netw. Comput., 2021
2020
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020