Shunbin Li

Orcid: 0000-0002-9350-0287

According to our database1, Shunbin Li authored at least 13 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Modeling and Analysis of Waferscale Switching Network with Multiple System Faults.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Mangling Rules Generation With Density-Based Clustering for Password Guessing.
IEEE Trans. Dependable Secur. Comput., 2023

Research on WLAN scenario optimisation policy based on IoT smart campus.
Int. J. Inf. Commun. Technol., 2023

2022
Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Security Enhancement Through Compiler-Assisted Software Diversity With Deep Reinforcement Learning.
Int. J. Digit. Crime Forensics, 2022

High-Performance Password Recovery Hardware Going From GPU to Hybrid CPU-FPGA Platform.
IEEE Consumer Electron. Mag., 2022

2021
Value Iteration Algorithm for Nonlinear Continuous-time Nonzero-Sum Games.
Proceedings of the 2021 International Conference on Security, 2021

An Adaptive Swarm Intelligence-Based Task Scheduling Framework for Heterogeneous IoT Systems.
Proceedings of the ICNCC 2021: The 10th International Conference on Networks, Communication and Computing, Beijing, China, December 10, 2021

Random Parameter Normalization Technique for Mimic Defense Based on Multi-queue Architecture.
Proceedings of the Artificial Intelligence and Security - 7th International Conference, 2021

2019
An Energy-Efficient Accelerator Based on Hybrid CPU-FPGA Devices for Password Recovery.
IEEE Trans. Computers, 2019

Energy-Efficient RAR3 Password Recovery with Dual-Granularity Data Path Strategy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2017
An Adaptive PAM-4 Analog Equalizer With Boosting-State Detection in the Time Domain.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2015
A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015


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