Shun Nagata

According to our database, Shun Nagata authored at least 3 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC.

Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET.

Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2021

A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW.

Ewout Martens, Davide Dermit, Mithlesh Shrivas, Shun Nagata, Jan Craninckx

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021