Shumpei Kawasaki
According to our database1,
Shumpei Kawasaki
authored at least 5 papers
between 1986 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
1990
1995
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2005
2010
2015
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018
1995
1989
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming.
IEEE Micro, 1989
1986
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986
A User-Adaptable VLSI Engine for Artificial Intelligence.
Proceedings of the Information Processing 86, 1986