Shuli Gao

According to our database, Shuli Gao authored at least 17 papers between 2006 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Efficient Realization of BCD Multipliers Using FPGAs.

Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini

Int. J. Reconfigurable Comput., 2017

Random channel generator of the integrated power line communication and visible light communication.

Shuli Gao, Jian Zhang, Jian Song, Hui Yang, Xi Chu

Proceedings of the IEEE International Symposium on Power Line Communications and its Applications, 2017

Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier.

Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini

Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016

Factors affecting the performance of knowledge collaboration in virtual team based on capital appreciation.

Shuli Gao, Yanli Guo, Jianbin Chen, Lin Li

Inf. Technol. Manag., 2016

2014

FPGA implementation of multiple Pursuit-Evasion games with decentralized Learning Automata.

Shuli Gao, Sidney N. Givigi, Alain J. G. Beaulieu

Proceedings of the IEEE International Systems Conference, 2014

2012

Asymmetric large size multipliers with optimised FPGA resource utilisation.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois

IET Comput. Digit. Tech., 2012

An improved BCD adder using 6-LUT FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

A Highly Sensitive and Selective Competition Assay for the Detection of Cysteine Using Mercury-Specific DNA, Hg²⁺ and Sybr Green I.

Hui Xu, Shuli Gao, Quanwen Liu, Dun Pan, Lihua Wang, Shuzhen Ren, Min Ding, Jingwen Chen, Gang Liu

Sensors, 2011

Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

J. Signal Process. Syst., 2010

2009

Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Int. J. Reconfigurable Comput., 2009

Two level decomposition based matrix multiplication for FPGAs.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007

Optimised realisations of large integer multipliers and squarers using embedded blocks.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

IET Comput. Digit. Tech., 2007

FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers.

Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers.

Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois

Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006