Shuichi Tahara

According to our database¹, Shuichi Tahara authored at least 8 papers between 1989 and 2007.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions to superconducting digital integrated circuits and single-flux quantum electronics.".

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2007

A 16-Mb Toggle MRAM With Burst Modes.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

MRAM Cell Technology for Over 500-MHz SoC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

MRAM Applications Using Unlimited Write Endurance.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2007

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2007

TD: Emerging Devices Devices and Circuits.

[BibT_eX]

[DOI]

Eugenio Cantatore

Shuichi Tahara

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2003

Resistance ratio read (R<sup>3</sup>) architecture for a burst operated 1.5V MRAM macro.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

1989

570-ps 13-mW Josephson 1-kbit NDRO RAM.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, October, 1989

Shuichi Tahara

Awards

IEEE Fellow

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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