Shuhei Tanakamaru
According to our database1,
Shuhei Tanakamaru
authored at least 23 papers
between 2010 and 2016.
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Bibliography
2016
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.
IEEE J. Solid State Circuits, 2016
Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths.
IEICE Trans. Electron., 2016
2015
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs).
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories.
IEICE Trans. Electron., 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten.
Proceedings of the Symposium on VLSI Circuits, 2015
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs).
IEEE J. Solid State Circuits, 2013
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming.
IEEE J. Solid State Circuits, 2012
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor.
IEICE Trans. Electron., 2012
Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs).
IEICE Electron. Express, 2012
Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 0.5 V Operation V <sub>TH</sub> Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems.
IEEE J. Solid State Circuits, 2011
Improvement of Read Margin and Its Distribution by V<sub>TH</sub> Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection.
IEEE J. Solid State Circuits, 2011
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010