Shubham Sahay

Orcid: 0000-0001-9992-3240

According to our database1, Shubham Sahay authored at least 16 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

Efficient Reinforcement Learning On Passive RRAM Crossbar Array.
CoRR, 2024

2023
A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

An Automatic Leakage Compensation Technique for Capacitively Coupled Class-AB Operational Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Analytical Modeling of 3D NAND Flash Cell With a Gaussian Doping Profile.
IEEE Access, 2022

2021
3D-aCortex: an ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories.
Neuromorph. Comput. Eng., 2021

Energy-Efficient Implementation of Generative Adversarial Networks on Passive RRAM Crossbar Arrays.
CoRR, 2021

Long Short-Term Memory Implementation Exploiting Passive RRAM Crossbar Array.
CoRR, 2021

A Flash-Based Multi-Bit Content-Addressable Memory with Euclidean Squared Distance.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

2020
Efficient Mixed-Signal Neurocomputing Via Successive Integration and Rescaling.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Mixed-Signal Vector-by-Matrix Multiplier Circuits Based on 3D-NAND Memories for Neurocomputing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Time-Domain Mixed-Signal Vector-by-Matrix Multiplier Exploiting 1T-1R Array.
CoRR, 2019

2018
A Behavioral Compact Model of 3D NAND Flash Memory.
CoRR, 2018

Switching-Time Dependent PUF Using STT-MRAM.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017
Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs.
IEEE Access, 2017


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