Shubham Rai

Orcid: 0000-0002-6522-5628

According to our database1, Shubham Rai authored at least 40 papers between 2018 and 2024.

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Bibliography

2024
Thwarting GNN-Based Attacks Against Logic Locking.
IEEE Trans. Inf. Forensics Secur., 2024

Accelerating Automated Driving and ADAS Using HW/SW Codesign.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers.
IEEE Embed. Syst. Lett., December, 2023

Design of Energy-Efficient RFET-Based Exact and Approximate 4:2 Compressors and Multipliers.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Formal Analysis of Camouflaged Reconfigurable Circuits.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Discerning Limitations of GNN-based Attacks on Logic Locking.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits.
IEEE Trans. Emerg. Top. Comput., 2022

Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy.
IEEE Des. Test, 2022

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Securing Hardware through Reconfigurable Nano-Structures.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Improving Technology Mapping for And-Inverter-Cones.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysis.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A Versatile Mapping Approach for Technology Mapping and Graph Optimization.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture".
IEEE Open J. Circuits Syst., 2021

RECON: Resource-Efficient CORDIC-Based Neuron Architecture.
IEEE Open J. Circuits Syst., 2021

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies.
IEEE Access, 2021

END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021


Perspectives on Emerging Computation-in-Memory Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
A CORDIC Based Configurable Activation Function for ANN Applications.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Exploiting Emerging Reconfigurable Technologies for Secure Devices.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Emerging reconfigurable nanotechnologies: can they support future electronics?
Proceedings of the International Conference on Computer-Aided Design, 2018

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology mapping flow for emerging reconfigurable silicon nanowire transistors.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018


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