Shubha Bommalingaiahnapallya

According to our database, Shubha Bommalingaiahnapallya authored at least 5 papers between 2004 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

A 3, times, 5-Gb/s Multilane Low-Power 0.18-muhbox m CMOS Pseudorandom Bit Sequence Generator.

Kin-Joe Sham, Shubha Bommalingaiahnapallya, Mahmoud Reza Ahmadi, Ramesh Harjani

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator.

Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

Power optimized LC VCO and mixer co-design.

Byunghoo Jung, Shubha Bommalingaiahnapallya, Ramesh Harjani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Process tolerant design of N-tone Sigma-Delta converters.

Shubha Bommalingaiahnapallya, Ramesh Harjani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Low power implementation of an n-tone Sigma Delta converter.

Shubha Bommalingaiahnapallya, Ramesh Harjani

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004