Shuai Wang
Affiliations:- Nanjing University, Department of Computer Science and Technology, China
- New Jersey Institute of Technology, Department of Electrical and Computer Engineering, Newark, NJ, USA (PhD 2010)
According to our database1,
Shuai Wang
authored at least 23 papers
between 2005 and 2017.
Collaborative distances:
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Bibliography
2017
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime.
ACM Trans. Design Autom. Electr. Syst., 2017
2016
J. Circuits Syst. Comput., 2016
2015
On the characterization and optimization of system-level vulnerability for instruction caches in embedded processors.
Microprocess. Microsystems, 2015
2014
Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures.
IET Comput. Digit. Tech., 2012
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors.
IEEE Trans. Computers, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Asymmetrically banked value-aware register files for low-energy and high-performance.
Microprocess. Microsystems, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
2006
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006
In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006
2005
Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005