Shu-Yu Jiang
According to our database1,
Shu-Yu Jiang
authored at least 8 papers
between 2001 and 2011.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2011
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator.
IEEE Trans. Very Large Scale Integr. Syst., 2011
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
Static divided word matching line for low-power Content Addressable Memory design.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001