Shu-Hsuan Chou

According to our database1, Shu-Hsuan Chou authored at least 11 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems.
IEEE Trans. Computers, 2012

2011
Hierarchical circuit-switched NoC for multicore video processing.
Microprocess. Microsystems, 2011

A Novel mechanism for speed characterization during delay test.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010
RunAssert: A non-intrusive run-time assertion for parallel programs debugging.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
VisoMT: A Collaborative Multithreading Multicore Processor for Multimedia Applications With a Fast Data Switching Mechanism.
IEEE Trans. Circuits Syst. Video Technol., 2009

VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

dIP: A Non-intrusive Debugging IP for Dynamic Data Race Detection in Many-Core.
Proceedings of the 10th International Symposium on Pervasive Systems, 2009

NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core.
Proceedings of the 46th Design Automation Conference, 2009

No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips.
Proceedings of the 46th Design Automation Conference, 2009

2007
An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model.
Proceedings of the 44th Design Automation Conference, 2007

2006
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006


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