Shrutisagar Chandrasekaran

According to our database, Shrutisagar Chandrasekaran authored at least 14 papers between 2005 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2009

Efficient systolic architecture and power modeling for finite ridgelet transform.

Abdul Naser Sazish, Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the 12th IEEE International Conference on Computer Vision Workshops, 2009

2008

FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.

Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira

IEEE Trans. Signal Process., 2008

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform.

Shrutisagar Chandrasekaran, Abbes Amira, Minghua Shi, Amine Bermak

J. Real Time Image Process., 2008

A segmentation concept for positron emission tomography imaging using multiresolution analysis.

Abbes Amira, Shrutisagar Chandrasekaran, David W. G. Montgomery, Isa Servan Uzun

Neurocomputing, 2008

High Performance FPGA Implementation of the Mersenne Twister.

Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing.

Abbes Amira, Shrutisagar Chandrasekaran

IEEE Trans. Very Large Scale Integr. Syst., 2007

Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms.

Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A New Behavioural Power Modelling Approach for FPGA based Custom Cores.

Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006

An Efficient FPGA Implementation of Gaussian Mixture Models-Based Classifier Using Distributed Arithmetic.

Minghua Shi, Amine Bermak, Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Power Modeling and Efficient FPGA Implementation of Color Space Conversion.

Faycal Bensaali, Abbes Amira, Shrutisagar Chandrasekaran

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling.

Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Implementation and Power Modelling of the Fast Walsh Transform.

Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

An area efficient low power inner product computation for discrete orthogonal transforms.

Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the 2005 International Conference on Image Processing, 2005

High Speed / Low Power Architectures for the Finite Radon Transform.

Shrutisagar Chandrasekaran, Abbes Amira

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005