Shrirang K. Karandikar

According to our database, Shrirang K. Karandikar authored at least 10 papers between 2003 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

FIRA - a novel method for benchmarking the cache hierarchy.

Varad R. Deshmukh, Nishchay S. Mhatre, Shrirang K. Karandikar

Proceedings of the 5th ACM COMPUTE Conference: Intelligent & scalable system technologies, 2012

2008

Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.

Shrirang K. Karandikar, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.

Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.

Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz

Proc. IEEE, 2007

The nuts and bolts of physical synthesis.

Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Fast Electrical Correction Using Resizing and Buffering.

Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005

Fast comparisons of circuit implementations.

Shrirang K. Karandikar, Sachin S. Sapatnekar

IEEE Trans. Very Large Scale Integr. Syst., 2005

Fast estimation of area-delay trade-offs in circuit sizing.

Shrirang K. Karandikar, Sachin S. Sapatnekar

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Logical effort based technology mapping.

Shrirang K. Karandikar, Sachin S. Sapatnekar

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.

Shrirang K. Karandikar, Sachin S. Sapatnekar

IEEE Trans. Very Large Scale Integr. Syst., 2003