Shreyas Nandi

According to our database1, Shreyas Nandi authored at least 2 papers between 2020 and 2021.

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Bibliography

2021
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.
Proceedings of the IEEE International Test Conference, 2020


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