Shrestha Bansal

According to our database, Shrestha Bansal authored at least 5 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Neural-Network Based Self-Initializing Algorithm for Multi-Parameter Optimization of High-Speed ADCs.

Shrestha Bansal, Erfan Ghaderi, Chase Puglisi, Subhanshu Gupta

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS.

Erfan Ghaderi, Chase Puglisi, Shrestha Bansal, Subhanshu Gupta

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 2Vpk-pk, diff Input Range 1GS/s Voltage-to-Time Converter with Tunable Distortion Compensation.

Chase Puglisi, Erfan Ghaderi, Shrestha Bansal, George LaRue, Subhanshu Gupta

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017

Digital LDO with analog-assisted dynamic reference correction for fast and accurate load regulation.

Abhirup Lahiri, Shrestha Bansal, Nitin Bansal, Mohammad S. Hashmi

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Energy Efficient NoC Router for High Throughput Applications in Many-Core GPUs.

Shrestha Bansal, Hemanta Kumar Mondal, Sri Harsha Gade, Sujay Deb

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017