Shreekant S. Thakkar

According to our database1, Shreekant S. Thakkar authored at least 19 papers between 1986 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2024
Enhancing Autonomous System Security and Resilience With Generative AI: A Comprehensive Survey.
IEEE Access, 2024

1999
Internet Streaming SIMD Extensions.
Computer, 1999

1996
Multiprocessor Validation of the Pentium Pro.
Computer, 1996

Multiprocessor Validation of the Pentium® Pro Microprocessor.
Proceedings of the Forty-First IEEE Computer Society International Conference: Technologies for the Information Superhighway, 1996

1994
Enabling Multiprocessor Technology: Introduction.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1992
Tuning a Parallel Database Algorithm on a Shared-memory Multiprocessor.
Softw. Pract. Exp., 1992

1990
Scalable Shared-Memory Multiprocessor Architectures.
Computer, 1990

Synchronization Algorithms for Shared-Memory Multiprocessors.
Computer, 1990

Cache Architectures in Tightly Coupled Multiprocessors - Guest Editors' Introduction to the Special Issue.
Computer, 1990

Performance of an OLTP Application on Symmetry Multiprocessor System.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

1989
Parallel Programming: Harnessing the Hardware - Guest Editor's Introduction.
IEEE Softw., 1989

1988
Guest Editor's Introduction: Parallel Programming—Issues and Questions.
IEEE Softw., 1988

Programming Three Parallel Computers.
IEEE Softw., 1988

The Balance multiprocessor system.
IEEE Micro, 1988

The Symmetry Multiprocessor System.
Proceedings of the International Conference on Parallel Processing, 1988

1987
Experience with Three Parallel Programming Systems.
Proceedings of the COMPCON'87, 1987

VLSI Assist For a Multiprocessor.
Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), 1987

1986
The cognitive architecture project.
SIGARCH Comput. Archit. News, 1986

An Instruction Fetch Unit for a Graph Reduction Machine.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986


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