Shourya Gupta
Orcid: 0009-0009-5825-2394
According to our database1,
Shourya Gupta
authored at least 15 papers
between 2017 and 2024.
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Bibliography
2024
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024
Proceedings of the 7th Joint International Conference on Data Science & Management of Data (11th ACM IKDD CODS and 29th COMAD), 2024
2023
QuCardio: Application of Quantum Machine Learning for Detection of Cardiovascular Diseases.
IEEE Access, 2023
2022
NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Proceedings of the Applications and Techniques in Information Security, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability.
Microelectron. J., 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation.
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
2019
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Pentavariate V<sub>min</sub> Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017