Shounak Chakraborty

According to our database, Shounak Chakraborty authored at least 27 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment.

Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Magnus Själander, Klaus D. McDonald-Maier

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores.

Shounak Chakraborty, Yanshul Sharma, Sanjay Moulik

ACM Trans. Embed. Comput. Syst., July, 2024

TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture.

Sukarn Agarwal, Shounak Chakraborty, Magnus Själander

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing.

Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore.

Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier

IEEE Trans. Parallel Distributed Syst., February, 2023

NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems.

Shounak Chakraborty, Mehdi Safarpour, Olli Silvén

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR).

Sukarn Agarwal, Shounak Chakraborty, Magnus Själander

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

ETA-HP: an energy and temperature-aware real-time scheduler for heterogeneous platforms.

Yanshul Sharma, Shounak Chakraborty, Sanjay Moulik

J. Supercomput., 2022

ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches.

Sangeet Saha, Shounak Chakraborty, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore.

Yanshul Sharma, Sanjay Moulik, Shounak Chakraborty

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

STIFF: thermally safe temperature effect inversion aware FinFET based multi-core.

Shounak Chakraborty, Vassos Soteriou, Magnus Själander

Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2021

Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization.

Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier

ACM Trans. Embed. Comput. Syst., 2021

WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption.

Shounak Chakraborty, Magnus Själander

ACM Trans. Archit. Code Optim., 2021

SEAMERS: A Semi-partitioned Energy-Aware scheduler for heterogeneous MulticorEReal-time Systems.

Sanjay Moulik, Zinea Das, Rajesh Devaraj, Shounak Chakraborty

J. Syst. Archit., 2021

ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache.

Sukarn Agarwal, Shounak Chakraborty

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

RePAiR: A Strategy for Reducing Peak Temperature while Maximising Accuracy of Approximate Real-Time Computing: Work-in-Progress.

Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

2019

Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design.

Shounak Chakraborty, Hemangee K. Kapoor

ACM Trans. Design Autom. Electr. Syst., 2019

2018

Analysing the Role of Last Level Caches in Controlling Chip Temperature.

Shounak Chakraborty, Hemangee K. Kapoor

IEEE Trans. Sustain. Comput., 2018

Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors.

Ashwini A. Kulkarni, Shounak Chakraborty, Shrinivas P. Mahajan, Hemangee K. Kapoor

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs.

Shounak Chakraborty, Hemangee K. Kapoor

Microprocess. Microsystems, 2017

Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors.

Shounak Chakraborty, Hemangee K. Kapoor

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016

Static energy reduction by performance linked dynamic cache resizing.

Shounak Chakraborty, Hemangee K. Kapoor

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs.

Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

2015

Power aware cache miss reduction by energy efficient victim retention.

Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Static energy reduction by performance linked cache capacity management in tiled CMPs.

Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty

Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks.

Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

2014

A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip.

Narendra Kumar Meena, Hemangee K. Kapoor, Shounak Chakraborty

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014