Shoun Matsunaga

According to our database, Shoun Matsunaga authored at least 16 papers between 2007 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.

Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme.

Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM.

Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Soft-Delay-Error Evaluation in Content-Addressable Memory.

Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure.

Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013

High-throughput CAM based on a synchronous overlapped search scheme.

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

IEICE Electron. Express, 2013

2012

A 3.14 um² 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.

Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Symposium on VLSI Circuits, 2012

Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction.

Magdalena Sihotang, Shoun Matsunaga, Takahiro Hanyu

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM.

Shoun Matsunaga, Takahiro Hanyu

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.

Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme.

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2009

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues.

Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Design, Automation and Test in Europe, 2009

2007

Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic.

Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007