Shoji Yamahata

According to our database, Shoji Yamahata authored at least 4 papers between 1996 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Emitter-metal-related degradation in InP-based HBTs operating at high current density and its suppression by refractory metal.

Yoshino K. Fukai, Kenji Kurishima, Norihide Kashio, Minoru Ida, Shoji Yamahata, Takatomo Enoki

Microelectron. Reliab., 2009

2008

Highly Reliable Submicron InP-Based HBTs with over 300-GHz <i>f</i>_t.

Norihide Kashio, Kenji Kurishima, Yoshino K. Fukai, Shoji Yamahata

IEICE Trans. Electron., 2008

2004

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector.

Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi

IEEE J. Solid State Circuits, 2004

1996

Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems.

Makoto Nakamura, Yuhki Imai, Shoji Yamahata, Yohtaro Umeda

IEEE J. Solid State Circuits, 1996