Shoji Shukuri

According to our database, Shoji Shukuri authored at least 9 papers between 1989 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2002

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit.

Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi

IEEE J. Solid State Circuits, 2002

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001

CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip.

Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1992

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki

IEEE J. Solid State Circuits, March, 1992

1991

Quasi-complementary BiCMOS for sub-3-V digital circuits.

Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, November, 1991

On-Chip Multiple Superscalar Processors with Secondary Cache Memories.

M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Takashi Nishida

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990

The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits.

Takehisa Hayashi, Toshio Doi, Mitsuo Asai, Kenichi Ishibashi, Shoji Shukuri, Atsuo Watanabe, Makoto Suzuki

IEEE J. Solid State Circuits, April, 1990

1989

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM.

Makoto Suzuki, Suguru Tachibana, Atsuo Watanabe, Shoji Shukuri, Hisayuki Higuchi, Takahiro Nagano, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989

A feedback-type BiCMOS logic gate.

Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watnabe, Shoji Shukuri, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989