Shoji Shukuri

According to our database, Shoji Shukuri authored at least 5 papers between 1989 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2002

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit.

Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi

IEEE J. Solid State Circuits, 2002

2001

A multigigabit DRAM technology with 6F² open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh

IEEE J. Solid State Circuits, 2001

CMOS process compatible ie-Flash (inverse gate electrode Flash) technology for system-on-a-chip.

Shoji Shukuri, Kazumasa Yanagisawa, Koichiro Ishibashi

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1989

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM.

Makoto Suzuki, Suguru Tachibana, Atsuo Watanabe, Shoji Shukuri, Hisayuki Higuchi, Takahiro Nagano, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989

A feedback-type BiCMOS logic gate.

Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watnabe, Shoji Shukuri, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989