Shoichiro Kawashima

According to our database, Shoichiro Kawashima authored at least 9 papers between 1988 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology.

Shoichiro Kawashima, Keizo Morita, Mitsuharu Nakazawa, Kazuaki Yamane, Mitsuhiro Ogai, Kuninori Kawabata, Kazuaki Takai, Yasuhiro Fujii, Ryoji Yasuda, Wensheng Wang, Yukinobu Hikosaka, Ken'ichi Inoue

IEICE Trans. Electron., 2015

2007

A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip.

Shoichiro Kawashima, Isao Fukushi, Keizo Morita, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Kazuaki Yamane, Tomohisa Hirayama, Toru Endo

IEICE Trans. Electron., 2007

2004

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM).

Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima

IEEE J. Solid State Circuits, 2004

2003

A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories.

Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima

IEEE J. Solid State Circuits, 2003

A ferroelectric memory-based secure dynamically programmable gate array.

Shoichi Masui, Tsuzumi Ninomiya, Michiya Oura, Wataru Yokozeki, Kenji Mukaida, Shoichiro Kawashima

IEEE J. Solid State Circuits, 2003

2002

Bitline GND sensing technique for low-voltage operation FeRAM.

Shoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki

IEEE J. Solid State Circuits, 2002

A 16 kb 1T1C FeRAM test chip using current-based reference scheme.

Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1998

A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's.

Shoichiro Kawashima, Toshihiko Mori, Ryuhei Sasagawa, Makoto Hamaminato, Shigetoshi Wakayama, Kazuo Sukegawa, Isao Fukushi

IEEE J. Solid State Circuits, 1998

1988

A 46-ns 1-Mbit CMOS SRAM.

Hiroshi Shimada, Shoichiro Kawashima, Hideo Itoh, Noriyuki Suzuki, Takashi Yabu

IEEE J. Solid State Circuits, February, 1988