Shoichiro Kawashima

According to our database1, Shoichiro Kawashima authored at least 9 papers between 1988 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2015
An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology.
IEICE Trans. Electron., 2015

2007
A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip.
IEICE Trans. Electron., 2007

2004
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM).
IEEE J. Solid State Circuits, 2004

2003
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories.
IEEE J. Solid State Circuits, 2003

A ferroelectric memory-based secure dynamically programmable gate array.
IEEE J. Solid State Circuits, 2003

2002
Bitline GND sensing technique for low-voltage operation FeRAM.
IEEE J. Solid State Circuits, 2002

A 16 kb 1T1C FeRAM test chip using current-based reference scheme.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1998
A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's.
IEEE J. Solid State Circuits, 1998

1988
A 46-ns 1-Mbit CMOS SRAM.
IEEE J. Solid State Circuits, February, 1988


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