Shoichi Masui

According to our database1, Shoichi Masui authored at least 32 papers between 1983 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A unified multi-view multi-person tracking framework.
Comput. Vis. Media, February, 2023

A Unified Multi-view Multi-person Tracking Framework.
CoRR, 2023

Hard to Track Objects with Irregular Motions and Similar Appearances? Make It Easier by Buffering the Matching Space.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023

Is Weakly-Supervised Action Segmentation Ready for Human-Robot Interaction? No, Let's Improve It with Action-Union Learning.
IROS, 2023

2022
Hard to Track Objects with Irregular Motions and Similar Appearances? Make It Easier by Buffering the Matching Space.
CoRR, 2022

The Second-place Solution for ECCV 2022 Multiple People Tracking in Group Dance Challenge.
CoRR, 2022

The Second-place Solution for CVPR 2022 SoccerNet Tracking Challenge.
CoRR, 2022


2017
Foreword.
IEICE Trans. Electron., 2017

2016
19.2 cm<sup>3</sup> flexible fetal heart rate sensor for improved quality of pregnancy life.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications.
IEEE J. Biomed. Health Informatics, 2015

A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Radio channel characterization for 400 MHz implanted devices.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A WBAN 802.15.6 compliant multi-band re-configurable Transceiver for Medical Applicaitons.
Proceedings of the 9th International Conference on Body Area Networks, 2014

An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2012
Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS.
IEICE Electron. Express, 2012

A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer.
IEICE Electron. Express, 2012

Fractional-N PLL synthesizer with 15µsec start-up time by on-chip nonvolatile memory.
IEICE Electron. Express, 2012

2011
Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL.
IEICE Trans. Electron., 2011

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using <i>g<sub>m</sub></i>/<i>I<sub>D</sub></i> Lookup Table Methodology.
IEICE Trans. Electron., 2011

2009
Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers.
IEICE Trans. Electron., 2009

2007
A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology.
IEEE J. Solid State Circuits, 2007

2006
An area-efficient universal cryptography processor for smart cards.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM Technology.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory.
IEICE Trans. Electron., 2005

Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm.
IEICE Trans. Electron., 2005

2004
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM).
IEEE J. Solid State Circuits, 2004

2003
A ferroelectric memory-based secure dynamically programmable gate array.
IEEE J. Solid State Circuits, 2003

Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

1983
Decision-Making in Time-Critical Situations.
Proceedings of the 8th International Joint Conference on Artificial Intelligence. Karlsruhe, 1983


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