Sho Muroga
Orcid: 0000-0003-0567-4752
According to our database1,
Sho Muroga
authored at least 6 papers
between 2013 and 2020.
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Bibliography
2020
Effect of Complex Permeability on Circuit Parameters of CPW with Magnetic Noise Suppression Sheet.
IEICE Trans. Commun., 2020
IEICE Electron. Express, 2020
2015
Analysis of on-chip digital noise coupling path for wireless communication IC test chip.
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015
2014
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator.
IEICE Trans. Electron., 2014
2013
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013