Sho Ikeda

According to our database, Sho Ikeda authored at least 14 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Hierarchical Light Sampling with Accurate Spherical Gaussian Lighting.

Yusuke Tokuyoshi, Sho Ikeda, Paritosh Kulkarni, Takahiro Harada

Proceedings of the SIGGRAPH Asia 2024 Conference Papers, 2024

2022

Fused BVH to Ray Trace Level of Detail Meshes.

Paritosh Kulkarni, Sho Ikeda, Takahiro Harada

Proceedings of the SIGGRAPH Asia 2022 Posters, 2022

2017

A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique.

Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu

IEEE J. Solid State Circuits, 2017

Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.

Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique.

Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna.

Yosuke Ishikawa, Sang-yeop Lee, Shin Yonezawa, Sho Ikeda, Yiming Fang, Taisuke Hamada, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network.

Sho Ikeda, Sang-yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS.

Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

IEICE Trans. Electron., 2014

A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET.

Sho Ikeda, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor.

Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Performance Improvement of Physically Based Spectral Rendering Using Stochastic Sampling.

Shin Watanabe, Shota Kanamori, Sho Ikeda, Bisser Raytchev, Toru Tamaki, Kazufumi Kaneda

Proceedings of the Computational Color Imaging - 4th International Workshop, 2013

2012

A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS.

Sang-yeop Lee, Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

IEICE Trans. Electron., 2012

Optimal design method for chip-area-efficient CMOS low-dropout regulator.

Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS.

Norifumi Kanemaru, Sho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Proceedings of the International SoC Design Conference, 2011