We stand with Ukraine

We stand with Ukraine

Shlomo Weiss

Orcid: 0000-0002-0341-2743

According to our database¹, Shlomo Weiss authored at least 62 papers between 1983 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

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Links

On csauthors.net:

Bibliography

2021

A novel low power hybrid cache using GC-EDRAM cells.

[BibT_eX]

[DOI]

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Integr., 2021

2020

Perceptron based filtering of futile prefetches in embedded VLIW DSPs.

[BibT_eX]

[DOI]

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J. Syst. Archit., 2020

2018

SiMT-DSP: A Massively Multithreaded DSP Architecture.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2018

Decoupled Branch Predictor for Embedded DSP.

[BibT_eX]

[DOI]

Konstantin Berestizshevsky

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IEEE Embed. Syst. Lett., 2018

2016

An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation.

[BibT_eX]

[DOI]

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IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Deflection Routing in Hierarchical Mesh NoCs.

[BibT_eX]

[DOI]

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IEEE Embed. Syst. Lett., 2016

2015

DNOC: an accurate and fast virtual channel and deflection routing network-on-chip simulator.

[BibT_eX]

[DOI]

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Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

2014

L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters.

[BibT_eX]

[DOI]

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IEEE Trans. Very Large Scale Integr. Syst., 2014

Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators.

[BibT_eX]

[DOI]

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IEEE Trans. Computers, 2014

Computational methods for Conway's Game of Life cellular automaton.

[BibT_eX]

[DOI]

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J. Comput. Sci., 2014

Fast evaluation of a time-domain non-linear cochlear model on GPUs.

[BibT_eX]

[DOI]

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J. Comput. Phys., 2014

RIDER: Ring deflection router with buffers.

[BibT_eX]

[DOI]

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Des. Autom. Embed. Syst., 2014

2013

Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores.

[BibT_eX]

[DOI]

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ACM Trans. Archit. Code Optim., 2013

Phase-change memory: An architectural perspective.

[BibT_eX]

[DOI]

Omer Zilberberg

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ACM Comput. Surv., 2013

A Parallel Algorithm for a Physiological Non-Linear Model of the Cochlea.

[BibT_eX]

[DOI]

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Proceedings of the International Conference on Computational Science, 2013

2012

Complex Floating Point - A Novel Data Word Representation for DSP Processors.

[BibT_eX]

[DOI]

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IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Architectural virtualization extensions: A systems perspective.

[BibT_eX]

[DOI]

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Comput. Sci. Rev., 2012

Virtio network paravirtualization driver: Implementation and performance of a de-facto standard.

[BibT_eX]

[DOI]

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Comput. Stand. Interfaces, 2012

Buffered deflection routing for networks-on-chip.

[BibT_eX]

[DOI]

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Yitzhak (Tsahi) Birk

Proceedings of the 2012 Interconnection Network Architecture, 2012

Streamlined Network-on-Chip for Multicore Embedded Architectures.

[BibT_eX]

[DOI]

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Yitzhak (Tsahi) Birk

Proceedings of the Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28, 2012

2010

Branch target buffer design for embedded processors.

[BibT_eX]

[DOI]

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Microprocess. Microsystems, 2010

Reducing leakage power with BTB access prediction.

[BibT_eX]

[DOI]

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Integr., 2010

Low power branch prediction for embedded application processors.

[BibT_eX]

[DOI]

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Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009

Reexecution and Selective Reuse in Checkpoint Processors.

[BibT_eX]

[DOI]

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Trans. High Perform. Embed. Archit. Compil., 2009

Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture.

[BibT_eX]

[DOI]

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IEEE Trans. Circuits Syst. II Express Briefs, 2009

Checkpoint allocation and release.

[BibT_eX]

[DOI]

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ACM Trans. Archit. Code Optim., 2009

Service level agreement for multithreaded processors.

[BibT_eX]

[DOI]

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ACM Trans. Archit. Code Optim., 2009

2008

Hiding the misprediction penalty of a resource-efficient high-performance processor.

[BibT_eX]

[DOI]

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ACM Trans. Archit. Code Optim., 2008

Thrifty BTB: A comprehensive solution for dynamic power reduction in branch target buffers.

[BibT_eX]

[DOI]

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Microprocess. Microsystems, 2008

DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals.

[BibT_eX]

[DOI]

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IEEE Comput. Archit. Lett., 2008

2007

Fairness enforcement in switch on event multithreading.

[BibT_eX]

[DOI]

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ACM Trans. Archit. Code Optim., 2007

2006

Power-aware out-of-order issue logic in high-performance microprocessors.

[BibT_eX]

[DOI]

Yehuda Sadeh Weinraub

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Microprocess. Microsystems, 2006

Fairness and Throughput in Switch on Event Multithreading.

[BibT_eX]

[DOI]

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Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2004

Programming Windows NT device drivers to operate non-interrupting embedded devices.

[BibT_eX]

[DOI]

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Microprocess. Microsystems, 2004

Selective main memory compression by identifying program phase changes.

[BibT_eX]

[DOI]

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Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

2003

Embedded instruction memory in automotive engine controllers.

[BibT_eX]

[DOI]

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IEEE Trans. Veh. Technol., 2003

Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors.

[BibT_eX]

[DOI]

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IEEE Trans. Computers, 2003

Approximate prefix coding for system-on-a-chip programs.

[BibT_eX]

[DOI]

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J. Syst. Archit., 2003

Pattern Matching by means of Multi-Resolution Compression.

[BibT_eX]

[DOI]

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Proceedings of the 2003 Data Compression Conference (DCC 2003), 2003

2002

A PCI bus simulation framework and some simulation results on PCI standard 2.1 latency limitations.

[BibT_eX]

[DOI]

Ehud Finkelstein

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J. Syst. Archit., 2002

A study of CodePack: optimizing embedded code space.

[BibT_eX]

[DOI]

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Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001

HW/SW partitioning of an embedded instruction memory decompressor.

[BibT_eX]

[DOI]

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Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

1999

Microprocessor system buses: A case study.

[BibT_eX]

[DOI]

Ehud Finkelstein

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J. Syst. Archit., 1999

Extending PCI Performance Beyond the Desktop.

[BibT_eX]

[DOI]

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Ehud Finkelstein

Computer, 1999

1998

Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes.

[BibT_eX]

[DOI]

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IEEE Trans. Computers, 1998

Floating point micropipeline performance.

[BibT_eX]

[DOI]

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J. Syst. Archit., 1998

Branch Prediction Based on Universal Data Compression Algorithms.

[BibT_eX]

[DOI]

Eitan Federovsky

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Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1995

Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1994

PowerPC 601 and Alpha 21064: A Tale of Two RISCs.

[BibT_eX]

[DOI]

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Computer, 1994

1993

Optimizing a superscalar machine to run vector code.

[BibT_eX]

[DOI]

IEEE Parallel Distributed Technol. Syst. Appl., 1993

1992

Scalar Memory References in Pipelined Multiprocessors: A Performance Study.

[BibT_eX]

[DOI]

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IEEE Trans. Software Eng., 1992

Memory conflict resolution in vector supercomputers.

[BibT_eX]

[DOI]

J. Supercomput., 1992

1991

Multiple-Port Memory Access in Decoupled Architecture Processors.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1991

1990

A study of scalar compilation techniques for pipelined supercomputers.

[BibT_eX]

[DOI]

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ACM Trans. Math. Softw., 1990

1989

Scalar supercomputer architecture.

[BibT_eX]

[DOI]

Proc. IEEE, 1989

An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors.

[BibT_eX]

[DOI]

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

1986

A Simulation Study of Decoupled Architecture Computers.

[BibT_eX]

[DOI]

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Nicholas Y. Pang

IEEE Trans. Computers, 1986

DOSS: a storage system for design data.

[BibT_eX]

[DOI]

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Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1984

Instruction Issue Logic in Pipelined Supercomputers.

[BibT_eX]

[DOI]

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IEEE Trans. Computers, 1984

Design transaction management.

[BibT_eX]

[DOI]

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Proceedings of the 21st Design Automation Conference, 1984

Recovery of In-Memory Data Structures for Interactive Update Applications.

[BibT_eX]

Proceedings of the COMPCON'84, Digest of Papers, Twenty-Eighth IEEE Computer Society International Conference, San Francisco, California, USA, February 27, 1984

1983

Chip assemblers: Concepts and capabilities.

[BibT_eX]

[DOI]

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Proceedings of the 20th Design Automation Conference, 1983

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