Shizunori Matsumoto
According to our database1,
Shizunori Matsumoto
authored at least 5 papers
between 2001 and 2018.
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Bibliography
2018
Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs.
Sensors, 2018
2017
4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processing.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2005
1/<i>f</i>-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Trans. Electron., 2005
2001
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Correlation method of circuit-performance and technology fluctuations for improved design reliability.
Proceedings of ASP-DAC 2001, 2001