Shivendra Singh Parihar

Orcid: 0000-0001-7104-2396

According to our database1, Shivendra Singh Parihar authored at least 9 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID.
CoRR, 2024

Technology Mapping for Cryogenic CMOS Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.
IEEE Open J. Circuits Syst., 2023

5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.
Proceedings of the Device Research Conference, 2023

Design Automation for Cryogenic CMOS Circuits.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Self-Heating characterization and modeling of 5nm technology node FinFETs.
Proceedings of the Device Research Conference, 2022

2019
Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019


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