Shivendra Singh Parihar

According to our database, Shivendra Singh Parihar authored at least 8 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Technology Mapping for Cryogenic CMOS Circuits.

Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch, Robert Wille

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.

Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.

Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.

Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

IEEE Open J. Circuits Syst., 2023

5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.

Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

Proceedings of the Device Research Conference, 2023

Design Automation for Cryogenic CMOS Circuits.

Victor M. van Santen, Marcel Walter, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Robert Wille, Hussam Amrouch

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Self-Heating characterization and modeling of 5nm technology node FinFETs.

Shivendra Singh Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan

Proceedings of the Device Research Conference, 2022

2019

Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model.

Shivendra Singh Parihar, Ramchandra Gurjar

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019