Shivakumar Swaminathan

According to our database1, Shivakumar Swaminathan authored at least 6 papers between 2000 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2001
On Using Twisted-Ring Counters for Test Set Embedding in BIST.
J. Electron. Test., 2001

A deterministic scan-BIST architecture with application to field testing of high-availability systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Built-in self testing of high-performance circuits using twisted-ring counters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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