Shirshendu Das

According to our database, Shirshendu Das authored at least 47 papers between 2013 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

HTree: Hardware Trojan Attack on Cache Resizing Policies.

Atul Kumar, Shirshendu Das, Basant Subba

IEEE Embed. Syst. Lett., September, 2024

RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks.

Jaspinder Kaur, Shirshendu Das

ACM Trans. Design Autom. Electr. Syst., March, 2024

PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC.

Prabuddha Sinha, Krishna Pratik BV, Shirshendu Das, Venkata Kalyan Tavva

Proceedings of the International Symposium on Memory Systems, 2024

$\mathcal{F}lush+early\mathcal{R}\text{ELOAD}$: Covert Channels Attack on Shared LLC Using MSHR Merging.

Aditya S. Gangwar, Prathamesh Nitin Tanksale, Shirshendu Das, Sudeepta Mishra

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

edAttack: Hardware Trojan Attack on On-Chip Packet Compression.

Atul Kumar, Dipika Deb, Shirshendu Das, Palash Das

IEEE Des. Test, December, 2023

Variation aware power management for GPU memories.

Divyansh Maura, Tanmay Goel, Kaustav Goswami, Dip Sankar Banerjee, Shirshendu Das

Microprocess. Microsystems, February, 2023

TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks.

Jaspinder Kaur, Shirshendu Das

J. Syst. Archit., February, 2023

ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning.

Jaspinder Kaur, Shirshendu Das

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022

Process variation aware DRAM-Cache resizing.

Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu

J. Syst. Archit., 2022

BHT-NoC: Blaming Hardware Trojans in NoC Routers.

Bharat Bisht, Shirshendu Das

IEEE Des. Test, 2022

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design.

Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee

CoRR, 2022

WinDRAM: Weak rows as in-DRAM cache.

Sudershan Kumar, Prabuddha Sinha, Shirshendu Das

Concurr. Comput. Pract. Exp., 2022

Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly.

Samiksha Verma, Shirshendu Das, Vipul Bondre

Proceedings of the 2022 International Symposium on Memory Systems, 2022

A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices.

Kaustav Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee

Proceedings of the 2022 International Symposium on Memory Systems, 2022

PV-aware Replacement Policy for Two-level Shared Cache.

Bindu Agarwalla, Nilkanta Sahu, Shirshendu Das

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021

Towards Enhanced System Efficiency while Mitigating Row Hammer.

Kaustav Goswami, Dip Sankar Banerjee, Shirshendu Das

ACM Trans. Archit. Code Optim., 2021

Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors.

Bindu Agarwalla, Shirshendu Das, Nilkanta Sahu

J. Syst. Archit., 2021

A Survey on Cache Timing Channel Attacks for Multicore Processors.

Jaspinder Kaur, Shirshendu Das

J. Hardw. Syst. Secur., 2021

Efficient On-chip Communication for Neuromorphic Systems.

Shobhit Kumar, Shirshendu Das, Manaal Mukhtar Jamadar, Jaspinder Kaur

Proceedings of the 2021 IEEE SmartWorld, 2021

MAPCP: Memory Access Pattern Classifying Prefetcher.

Manaal Mukhtar Jamadar, Jaspinder Kaur, Shirshendu Das

Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

Towards Row Sensitive DRAM Refresh through Retention Awareness.

Tanmay Goel, Divyansh Maura, Kaustav Goswami, Shirshendu Das, Dip Sankar Banerjee

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

A Fairness Conscious Cache Replacement Policy for Last Level Cache.

Kousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache.

Anurag Agarwal, Jaspinder Kaur, Shirshendu Das

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019

Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines.

Dipika Deb, John Jose, Shirshendu Das, Hemangee K. Kapoor

J. Parallel Distributed Comput., 2019

State Preserving Dynamic DRAM Bank Re-Configurations for Enhanced Power Efficiency.

Kaustav Goswami, Hemanta Kumar Mondal, Shirshendu Das, Dip Sankar Banerjee

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018

Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors.

Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets.

Shirshendu Das, Hemangee K. Kapoor

IEEE Trans. Parallel Distributed Syst., 2017

Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor.

Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture.

Shirshendu Das, Hemangee K. Kapoor

ACM Trans. Design Autom. Electr. Syst., 2016

Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches.

Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Tag only storage for capacity optimised last level cache in chip multiprocessors.

Surajit Das, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs.

Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs.

Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 31st Annual ACM Symposium on Applied Computing, 2016

2015

Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs.

Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 28th International Conference on VLSI Design, 2015

An efficient searching mechanism for dynamic NUCA in chip multiprocessors.

Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Power aware cache miss reduction by energy efficient victim retention.

Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Static energy reduction by performance linked cache capacity management in tiled CMPs.

Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty

Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Dynamic associativity management using utility based way-sharing.

Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks.

Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

2014

Victim retention for reducing cache misses in tiled chip multiprocessors.

Shirshendu Das, Hemangee K. Kapoor

Microprocess. Microsystems, 2014

An Approach for Multicast Routing in Networks-on-Chip.

M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 2014 International Conference on Information Technology, 2014

RT-DVS for Power Optimization in Multiprocessor Real-Time Systems.

B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 2014 International Conference on Information Technology, 2014

2013

Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors.

Hemangee K. Kapoor, Praveen Kanakala, Malti Verma, Shirshendu Das

J. Supercomput., 2013

A formal framework for interfacing mixed-timing systems.

Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor

Integr., 2013

Random-LRU: A Replacement Policy for Chip Multiprocessors.

Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

Dynamic Associativity Management Using Fellow Sets.

Shirshendu Das, Hemangee K. Kapoor

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Towards a Better Cache Utilization Using Controlled Cache Partitioning.

Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor

Proceedings of the IEEE 11th International Conference on Dependable, 2013