Shiro Sakiyama

According to our database, Shiro Sakiyama authored at least 12 papers between 1994 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques.

Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho

IEEE J. Solid State Circuits, 2015

2013

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise.

Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.

Koji Obata, Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2010

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback.

Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho

IEEE J. Solid State Circuits, 2010

A 69.8 dB SNDR 3^rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver.

Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage.

Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.

Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System.

Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho

IEEE J. Solid State Circuits, 2008

2006

A 0.03mm² 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface.

Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi, Makoto Hattori

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution.

Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Mixed body bias techniques with fixed V_t and I_ds generation circuits.

Masaya Sumita, Shiro Sakiyama, Masayoshi Kinoshita, Yuta Araki, Yuichiro Ikeda, Kohei Fukuoka

IEEE J. Solid State Circuits, 2005

1994

Quantizer neuron model and neuroprocessor-named quantizer neuron chip.

Susumu Maruno, Toshiyuki Kohda, Hiroyuki Nakahira, Shiro Sakiyama, Masakatsu Maruyama

IEEE J. Sel. Areas Commun., 1994