Shiro Kamohara

According to our database, Shiro Kamohara authored at least 13 papers between 1999 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2017

SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive.

Takumi Hasegawa, Yoshiki Yamamoto, Hideki Makiyama, Hiroki Shinkawata, Shiro Kamohara, Yasuo Yamaguchi

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2015

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM.

Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Hideki Makiyama, Takumi Hasegawa, Yoshiki Yamamoto, Shinobu Okanishi, Keiichi Maekawa, Naoki Banno, Makoto Miyamura, Koichiro Okamoto, Noriyuki Iguchi, Hidekazu Oda, Shiro Kamohara, Yasushi Yamagata, Nobuyuki Sugii, Hiromitsu Hada, Yasuhiro Ogasahara

IEEE Micro, 2015

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode.

Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham

IEICE Trans. Electron., 2015

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process.

Duc-Hung Le, Nobuyuki Sugii, Shiro Kamohara, Xuan-Thuan Nguyen, Koichiro Ishibashi, Cong-Kha Pham

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM.

Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Hideki Makiyama, Takumi Hasegawa, Yoshiki Yamamoto, Shinobu Okanishi, Keiichi Maekawa, Naoki Banno, Makoto Miyamura, Koichiro Okamoto, Noriyuki Iguchi, Yasuhiro Ogasahara, Hidekazu Oda, Shiro Kamohara, Yasushi Yamagata, Nobuyuki Sugii, Hiromitsu Hada

Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology.

Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2011

A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis.

Chizu Matsumoto, Yuichi Hamamura, Yoshiyuki Tsunoda, Hiroshi Uozaki, Isao Miyazaki, Shiro Kamohara, Yoshiyuki Kaneko, Kenji Kanamitsu

IEICE Trans. Electron., 2011

2007

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node.

Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya

IEEE J. Solid State Circuits, 2007

2005

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme.

Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh

IEEE J. Solid State Circuits, 2005

2004

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes.

Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2002

Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure.

Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2000

Circuit performance oriented device optimization using BSIM3 pre-silicon model parameters.

Mikako Miyama, Shiro Kamohara

Proceedings of ASP-DAC 2000, 2000

1999

Pre-silicon parameter generation methodology using BSIM3 for device/circuit concurrent design.

Mikako Miyama, Shiro Kamohara, Mitsuru Hiraki, Kazunori Onozawa, Hisaaki Kunitomo

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999