Shiro Hosotani

According to our database, Shiro Hosotani authored at least 3 papers between 1990 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A cost effective HDTV decoder IC with integrated system controller, down converter, graphics engine and display processor.

Obed Duardo, Paul da Graca, Shiro Hosotani, Satoshi Sugawa, Hong Jiang

IEEE Trans. Consumer Electron., 1999

1994

A 10 bit 20 MS/s 3 V supply CMOS A/D converter.

Masao Ito, Takahiro Miki, Shiro Hosotani, Toshio Kumamoto, Yukihiro Yamashita, Masaki Kijima, Takashi Okuda, Keisuke Okada

IEEE J. Solid State Circuits, December, 1994

1990

An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption.

Shiro Hosotani, Takahiro Miki, Atsushi Maeda, Nobuharu Yazawa

IEEE J. Solid State Circuits, February, 1990