Shinya Takamaeda-Yamazaki

IEEE J. Solid State Circuits, 2021

Foreword.

[BibT_eX]

[DOI]

Shinya Takamaeda

IEICE Trans. Inf. Syst., 2021

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture.

[BibT_eX]

[DOI]

Kazutoshi Hirose

Jaehoon Yu

IEEE Access, 2021

An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising.

[BibT_eX]

[DOI]

Nobuho Hashimoto

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design.

[BibT_eX]

[DOI]

Yoshiki Fujiwara

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2020

A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks.

[BibT_eX]

[DOI]

Int. J. Netw. Comput., 2020

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes.

[BibT_eX]

[DOI]

Mototsugu Hamada

Tadahiro Kuroda

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.

[BibT_eX]

[DOI]

Kodai Ueyoshi

Kota Ando

Kazutoshi Hirose

Mototsugu Hamada

Tadahiro Kuroda

IEEE J. Solid State Circuits, 2019

FPGA-Based Annealing Processor with Time-Division Multiplexing.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2019

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2019

A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators.

[BibT_eX]

[DOI]

Yuki Hirayama

Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019

Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band.

[BibT_eX]

[DOI]

Proceedings of the 2019 Digital Image Computing: Techniques and Applications, 2019

DeltaNet: Differential Binary Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2018

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing.

[BibT_eX]

[DOI]

Hoang Gia Vu

Takashi Nakada

IEICE Trans. Inf. Syst., 2018

Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing.

[BibT_eX]

[DOI]

Aoi Tanibata

Alexandre Schmid

Complex., 2018

Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions.

[BibT_eX]

[DOI]

Proceedings of the IEEE Visual Communications and Image Processing, 2018

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS.

[BibT_eX]

[DOI]

Kodai Ueyoshi

Kota Ando

Kazutoshi Hirose

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration.

[BibT_eX]

[DOI]

Takeshi Shimada

Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

2017

Quantization Error-Based Regularization in Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Artificial Intelligence XXXIV, 2017

In-memory area-efficient signal streaming processor design for binary neural networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Symposium on Computing and Networking, 2017

A Time-Division Multiplexing Ising Machine on FPGAs.

[BibT_eX]

[DOI]

Kasho Yamamoto

Weiqiang Huang

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects.

[BibT_eX]

[DOI]

Aoi Tanibata

Alexandre Schmid

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing.

[BibT_eX]

[DOI]

Hoang Gia Vu

Takashi Nakada

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

Accelerating deep learning by binarized hardware.

[BibT_eX]

[DOI]

Proceedings of the 2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, 2017

2016

Performance Optimization of Light-Field Applications on GPU.

[BibT_eX]

[DOI]

Yuttakon Yuttakonkit

IEICE Trans. Inf. Syst., 2016

CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing.

[BibT_eX]

[DOI]

Hoang Gia Vu

Supasit Kajkamhaeng

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs.

[BibT_eX]

[DOI]

Keisuke Fujimoto

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs.

[BibT_eX]

[DOI]

Hiroshi Nakatsuka

Yuichiro Tanaka

IEICE Trans. Inf. Syst., 2015

Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators.

[BibT_eX]

[DOI]

Yoshikazu Inagaki

Jun Yao

IEICE Trans. Inf. Syst., 2015

A CGRA-Based Approach for Accelerating Convolutional Neural Networks.

[BibT_eX]

[DOI]

Masakazu Tanomoto

Jun Yao

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations.

[BibT_eX]

[DOI]

Shohei Takeuchi

Yuttakon Yuttakonkit

Proceedings of the Third International Symposium on Computing and Networking, 2015

Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

A framework for efficient rapid prototyping by virtually enlarging FPGA resources.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Ultrasmall: The smallest MIPS soft processor.

[BibT_eX]

[DOI]

Hiroshi Nakatsuka

Yuichiro Tanaka

Thiem Van Chu

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2012

Towards a Low-Power Accelerator of Many FPGAs for Stencil Computations.

[BibT_eX]

[DOI]

Ryohei Kobayashi

Proceedings of the Third International Conference on Networking and Computing, 2012

ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

An FPGA-based scalable simulation accelerator for tile architectures.

[BibT_eX]

[DOI]

Ryosuke Sasakawa

Yoshito Sakaguchi