Shinya Ito

Orcid: 0000-0001-5529-223X

According to our database1, Shinya Ito authored at least 14 papers between 2000 and 2021.

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Bibliography

2021
Nonlinear visuoauditory integration in the mouse superior colliculus.
PLoS Comput. Biol., 2021

2017
Impact of generator failures on photovoltaic energy curtailment in power systems with large-scale integration of photovoltaic generation.
Proceedings of the 2017 IEEE International Conference on Industrial and Information Systems, 2017

2016
High-Degree Neurons Feed Cortical Computations.
PLoS Comput. Biol., 2016

2011
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.
IEEE J. Solid State Circuits, 2011

2007
Consumed-energy-type-aware routing for wireless sensor networks.
Proceedings of the Wireless Telecommunications Symposium, 2007

Exponentially Aggressive Preservation of Nearly Depleted Nodes for Wireless Sensor Networks.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Concept set extraction with user session context.
Proceedings of the 45th Annual Southeast Regional Conference, 2007

2006
A method of digital watermarking by using the frequency masking effect.
Syst. Comput. Jpn., 2006

2004
The Microarchitecture of the CUE-v2 Processor: Enabling the Simultaneous Processing of Dataflow and Control-Flow Threads.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

2002
Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance.
Microelectron. Reliab., 2002

A Self-evolutionary Emulation Scheme for A Networking Oriented Data-driven Processor Architecture: CUE.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

2001
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.
IEEE J. Solid State Circuits, 2001

2000
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000


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