Shinya Honda
Orcid: 0000-0002-7878-3944
According to our database1,
Shinya Honda
authored at least 60 papers
between 2003 and 2021.
Collaborative distances:
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Bibliography
2021
Int. J. Parallel Program., 2021
2019
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System.
Proceedings of the 2019 IEEE SmartWorld, 2019
Proceedings of the IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2019
Proceedings of the AICCC 2019: 2nd Artificial Intelligence and Cloud Computing Conference, 2019
2018
Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018
2017
In-vehicle Distributed Time-critical Data Stream Management System for Advanced Driver Assistance.
J. Inf. Process., 2017
Proceedings of the 13th European Dependable Computing Conference, 2017
2016
A Map Database System for Route Navigation with Multiple Transit Points and Destination Points.
Proceedings of the 5th IIAI International Congress on Advanced Applied Informatics, 2016
2015
System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler.
J. Inf. Process., 2015
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip.
IPSJ Trans. Syst. LSI Des. Methodol., 2015
Proceedings of the 31st IEEE International Conference on Data Engineering, 2015
Proceedings of the 10th Asian Control Conference, 2015
2014
SIGARCH Comput. Archit. News, 2014
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs.
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Toward Data-Centric Software Architecture for Automotive Systems - Embedded Data Stream Processing Approach.
Proceedings of the 2014 IEEE 11th Intl Conf on Ubiquitous Intelligence and Computing and 2014 IEEE 11th Intl Conf on Autonomic and Trusted Computing and 2014 IEEE 14th Intl Conf on Scalable Computing and Communications and Its Associated Workshops, 2014
Proceedings of the 33rd IEEE International Symposium on Reliable Distributed Systems Workshops, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
2013
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks.
IPSJ Trans. Syst. LSI Des. Methodol., 2013
Inf. Media Technol., 2013
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs.
Int. J. Reconfigurable Comput., 2013
Proceedings of the 2013 IEEE 10th International Conference on Ubiquitous Intelligence and Computing and 2013 IEEE 10th International Conference on Autonomic and Trusted Computing, 2013
Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration.
Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013
2012
IPSJ Trans. Syst. LSI Des. Methodol., 2012
IEICE Trans. Inf. Syst., 2012
IEEE Embed. Syst. Lett., 2012
Convergent evolution in structural elements of proteins investigated using cross profile analysis.
BMC Bioinform., 2012
Proceedings of the Trust and Trustworthy Computing - 5th International Conference, 2012
Proceedings of the 15th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2012
Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
2011
Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International SoC Design Conference, 2011
2010
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Automatic communication synthesis with hardware sharing for design space exploration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
2009
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis.
J. Inf. Process., 2009
J. Comput. Aided Mol. Des., 2009
2008
IPSJ Trans. Syst. LSI Des. Methodol., 2008
Free Energy Landscape Analysis System Based on Parallel Molecular Dynamics Simulation.
Inf. Media Technol., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Practice and analysis of an extension course for training trainers of embedded software.
SIGBED Rev., 2007
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
2005
SIGBED Rev., 2005
IEICE Trans. Inf. Syst., 2005
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
2003
Proceedings of the 1st IEEE Workshop on Software Technologies for Future Embedded Systems, 2003
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device.
Proceedings of the 2003 Design, 2003
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device.
Proceedings of the Embedded Software for SoC, 2003