Shinobu Nagayama
Orcid: 0000-0002-4783-7487
According to our database1,
Shinobu Nagayama
authored at least 70 papers
between 2002 and 2024.
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Bibliography
2024
Functional Decomposition of Symmetric Multiple-Valued Functions and Their Compact Representation in Decision Diagrams.
IEICE Trans. Inf. Syst., 2024
Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024
A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation.
Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024
2023
IPSJ Trans. Syst. LSI Des. Methodol., 2023
FLAP, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
2022
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions.
J. Multiple Valued Log. Soft Comput., 2022
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
2021
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
2019
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
2018
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions.
FLAP, 2018
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the Database and Expert Systems Applications, 2018
2017
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions.
IEICE Trans. Inf. Syst., 2017
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
2014
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators.
J. Multiple Valued Log. Soft Comput., 2014
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components.
J. Multiple Valued Log. Soft Comput., 2014
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating.
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Int. J. Reconfigurable Comput., 2014
IEICE Trans. Inf. Syst., 2014
Proceedings of the Prague Stringology Conference 2014, Prague, Czech Republic, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
2013
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams.
IEICE Trans. Inf. Syst., 2010
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
2009
IEEE Trans. Computers, 2009
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions.
Proceedings of the ISMVL 2009, 2009
A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
A systolic regular expression pattern matching engine and its application to network intrusion detection.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Proceedings of the FPL 2008, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
A Proposal of RM QRM-MLD with Independent Adaptive Control of Surviving Symbol Replica Candidates for MIMO-OFDM System.
Proceedings of the 66th IEEE Vehicular Technology Conference, 2007
A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Proposal of QRM-MLD for Reduced Complexity of MLD to Detect MIMO Signals in Fading Environment.
Proceedings of the 64th IEEE Vehicular Technology Conference, 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
J. Multiple Valued Log. Soft Comput., 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
2002
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002