Shinji Yamaura

According to our database, Shinji Yamaura authored at least 6 papers between 2007 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

76- to 81-GHz CMOS Built-In Self-Test With 72-dB C/N and Less Than 1 ppm Frequency Tolerance for Multi-Channel Radar Applications.

Masato Kohtani, Tomotoshi Murakami, Yoshiyuki Utagawa, Tomoyuki Arai, Shinji Yamaura

IEEE J. Solid State Circuits, 2021

A 77-GHz 8RX3TX Transceiver for 250-m Long-Range Automotive Radar in 40-nm CMOS Technology.

Tomoyuki Arai, Tatsunori Usugi, Tomotoshi Murakami, Shuya Kishimoto, Yoshiyuki Utagawa, Masato Kohtani, Ikuma Ando, Kazuhiro Matsunaga, Chihiro Arai, Shinji Yamaura

IEEE J. Solid State Circuits, 2021

2014

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE.

Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets.

Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications.

Hiroyuki Nakamoto, Masahiro Kudo, Kimitoshi Niratsuka, Toshihiko Mori, Shinji Yamaura

Proceedings of the 38th European Solid-State Circuit conference, 2012

2007

A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology.

Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose

IEEE J. Solid State Circuits, 2007