Shinji Miyano
According to our database1,
Shinji Miyano
authored at least 33 papers
between 1995 and 2024.
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Bibliography
2024
Mitigation of Accuracy Degradation in 3D Flash Memory Based Approximate Nearest Neighbor Search with Binary Tree Balanced Soft Clustering for Retrieval-Augmented AI.
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024
2014
13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.
IEEE J. Solid State Circuits, 2013
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy.
IEEE J. Solid State Circuits, 2013
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress.
IEICE Trans. Electron., 2013
IEICE Trans. Electron., 2013
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
IEICE Trans. Electron., 2012
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor.
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.
Proceedings of the Symposium on VLSI Circuits, 2012
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Improvement of Read Margin and Its Distribution by V<sub>TH</sub> Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection.
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Statistical VTH shift variation self-convergence scheme using near threshold VWL injection for local electron injected asymmetric pass gate transistor SRAM.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.
IEEE J. Solid State Circuits, 2000
1999
1998
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator.
IEEE J. Solid State Circuits, 1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1995
IEEE J. Solid State Circuits, November, 1995